VLSI Terminology: Definition of process technology

Definition of: process technology 

With regard to digital integrated circuits, process technology refers to the particular method used to make silicon chips. The driving force behind the manufacture of integrated circuits is miniaturization, and process technology boils down to the size of the finished transistor and other components. The smaller the transistors, the more transistors in the same area, the faster they switch, the less energy they require and the cooler the chip runs (given equal numbers of transistors).

Measured in Nanometers
The size of the features (the elements that make up the structures on a chip) used to be measured in micrometers. A 3 µm process technology, also called a "technology node" and "process node," referred to a silicon chip with features three micrometers in size. Today, features are measured in nanometers. A 45 nm process technology refers to features 45 nm or 0.45 µm in size.

Elements Measured
Historically, the process technology referred to the length of the silicon channel between the source and drain terminals in field effect transistors (see FET). The sizes of other features are generally derived as a ratio of the channel length, where some may be larger than the channel size and some smaller. For example, in a 90 nm process, the length of the channel may be 90 nm, but the width of the gate terminal may be only 50 nm.

An Example of Progress
Consider that the process technology of the first 486 chip in 1989 was one micron (1,000 nanometers). By 2003, the state-of-the-art decreased to 90 nm ("90 nano"). In 15 years, feature sizes were reduced by slightly less than one millionth of a meter. What may seem like a minuscule, microscopic change to the casual observer took thousands of man years and billions of dollars worth of research and development. Note the huge variance in semiconductor feature sizes starting in the 1950s (see chart below).

Chips Are Nanotechnology
Intel introduced 45 nm processors in 2008. To understand how tiny 45 nanometers is, it would take two thousand 45 nm objects laid side-by-side to equal the thickness of one human hair.

In 2010, 32 nm chips were introduced, and feature sizes as low as 11 nm are expected in the future. For some time, chips have been in the realm of nanotechnology, which refers to elements 100 nanometers and smaller.

read more at http://www.pcmag.com/encyclopedia_term/0,2542,t=process+technology&i=49759,00.asp

Definition of: feature size

Definition of: feature size 

The size of the elements on a chip, which is designated by the "DRAM half pitch." The smallest feature size is generally smaller than the feature size for a technology generation (technology node). For example, the 180 nm technology generation will have gate lengths smaller than 180 nm.

Definition of: DRAM half pitch 

The common measure of the technology generation of a chip. It is half the distance between cells in a dynamic RAM memory chip. For example, in 2002, the DRAM half pitch had been reduced to 130 nm (.13 micron). By 2006, it had shrunk to 65 nm (.065 micron).

source :http://www.pcmag.com/encyclopedia_term/0,2542,t=feature+size&i=43075,00.asp

Meaning conquering

conqueringpresent participle of con·quer (Verb)

Verb:

Overcome and take control of (a place or people) by use of military force. Successfully overcome (a problem or weakness).

Download the admit card of UPSC CDS(Combined Defence Services Examination) 2012 (I)

Unlike past, from 2012 onwards  candidates will be able to download their exam admit card at UPSC website. Yes, you heard it. From now on even UPSC admit card will be available online.

Though little late but it seems that even UPSC is learning that it is much better to upload admit card on Internet, rather than sending it by post or asking the candidates to visit UPSC office physically for duplicate hall ticket. A press note which has appeared in The Times of India, main paper and not in Ascent has confirmed the same.

To Download Combined Defence Services Examination admit card  Click  here 

http://upsc.nic.in/onlineadmitcard/main.aspx for 12.02.2012 exam.

tags: upsc admit cards,CDS Hall Tickets ,CDS Admit cards, download   admit card  of UPSC CDS,

Meaning of flee

Verb:	Run away from a place or situation of danger: "a man was shot twice as he fled from five masked youths". Run away from (someone or something): "he was forced to flee the country".
Synonyms:	escape - run away - fly - abscond - get away - shun

Meaning of Bleak

Adjective:	(of an area of land) Lacking vegetation and exposed to the elements.
Noun:	A small silvery shoaling fish (genera Alburnus and Chalcalburnus) of the minnow family, found in Eurasian rivers.
Synonyms:	adjective.  dreary - gloomy - dismal - desolate noun.  ablet

Meaning of Slaughter

Slaughter may refer to

n.

1. The killing of animals especially for food.

2. The killing of a large number of people; a massacre: "I could not give my name to aid the slaughter in this war, fought on both sides for grossly material ends" (Sylvia Pankhurst).

tr.v. slaugh·tered, slaugh·ter·ing, slaugh·ters

1. To kill (animals) especially for food; butcher.

2.

a. To kill (people) in large numbers; massacre.

b. To kill in a violent or brutal manner

10th class Mathematics Paper Model Questions

                                                                   SSC-10th Mathematics Paper Model Questions

Following are the SSC Mathematics Model Questions in Paper 2 drawn from Model Question Papers. There are two parts in the question paper. Topics covered in these parts are Geometry, Analytical Geometry, Statistics, Trigonometry, Matrices and Computing. These are model questions only and represent the nature of questions asked in the 10th Class (Tenth Class) Public Examinations in Andhra Pradesh: 

SSC Mathematics Model paper
Paper - II ( Parts A and B ) (English Version)
Time: 2 .30 Hours - Max Marks: 50

Instructions: 1. Answer the questions under Part- A on a separate answer book. 2. Write the answers to the questions under Part-B on the question paper itself and attach it to the answer book of Part-A.

Time: 2 Hours - PART-A - Marks: 35

Section - I
Note: 1. Answer ANY FIVE questions choosing at least TWO from each of the following groups. 2. Each question carries TWO marks. 5 × 2 = 10

GROUP - A (Geometry, Analytical Geometry, Statistics)

1. Two poles of height 6 mts and 11mts stand vertically on a plane ground. If the distance between their feet is 12mts. Determine the distance between their tops.
2. Find the equation of the straight line passing through the point (1, -6) and whose product of the intercepts on the coordinate axes is 1.
3. Find the ratio in which the Y- axis divides the line - segment joining the points (-3, 2) and (6, 1)
4. The mean marks scored by 50 students is 80. On verification of data, it was found that the marks of one student were shown as 73 instead of 37. If corrected, find the new mean.

SECTION - II

Note: 1. Answer any FOUR of the following six questions. 2. Each question carries ONE mark. 4 × 1 = 4.
1. Find the slope of the line perpendicular to 5x-2y+4 = 0
2. State the Basic Proportionality Theorem.
3. Expand C.P.U.

SECTION- III

GROUP - A (Geometry, Analytical Geometry, Statistics)

Note: 1. Answer ANY FOUR questions choosing atleast two from each of the following groups. 2. Each question carries FOUR marks. 4 × 4 = 16
1. State and prove Pythagorean Theorem.
2. Find the area of the quadrilateral, whose vertices are (-1, 6), (-3, -9), (5, -8) and (3, 9).
3. Find the equation of the straight line perpendicular to the line joining the points (3, -5), (5, 7) and passing through (2, -3)
4. The following distribution of 100 individuals, according to their age is shown in the following table. Find the Median

GROUP - B
(Trigonometry, Matrices, Computing)
1. Solve the equation 3y = 4 - 2x and x = 4 by using Cramer's method.
2. Gopal purchased a radio set of Rs. 500 and sold it for Rs. 600. Execute a flow chart using this data to determine loss or gain and its percentage. 

SECTION- IV

Note: 1. Answer ANY ONE question from the following
1. The question carries FIVE marks. 1 × 5 = 5
2. Construct a cyclic quadrilateral ABCD, where AB = 3cm BC = 6cm, AC = 4cm and AD = 2cm.
3. The relation among Mean, Median and Mode is [ ]
A) Mean = 3 Mode - 2 Median B) Median = 3 Mean - 2 Mode
C) Mode = 3 Mean - 2 Median D) Mode = 3 Median - 2 Mean
4 Small transistors are used in -- generation of computers [ ]
A) First B) Second C) Third D) Fourth

Read more: http://www.apcollegeadmissions.com/2012/01/ssc-10th-mathematics-paper-2-model.html#ixzz1iPhbpE00

Definition of Metastability...

source:
		Definition of  Metastability :
		Whenever there are setup and hold time violations in any flip-flop, it enters a state where its output is unpredictable: this state is known as metastable state (quasi stable state); at the end of metastable state, the flip-flop settles down to either '1' or '0'. This whole process is known as metastability. In the figure below Tsu is the setup time and Th is the hold time. Whenever the input signal D does not meet the Tsu and Th of the given D flip-flop, metastability occurs.
		When a flip-flop is in metastable state, its output oscillate between '0' and '1' as shown in the figure below (here the flip-flop output settles down to '0') . How long it takes to settle down, depends on the technology of the flip-flop.
		If we look deep inside of the flip-flop we see that the quasi-stable state is reached when the flip-flop setup and hold times are violated. Assuming the use of a positive edge triggered "D" type flip-flop, when the rising edge of the flip-flop clock occurs at a point in time when the D input to the flip-flop is causing its master latch to transition, the flip-flop is highly likely to end up in a quasi-stable state. This rising clock causes the master latch to try to capture its current value while the slave latch is opened allowing the Q output to follow the "latched" value of the master. The most perfectly "caught" quasi-stable state (on the very top of the hill) results in the longest time required for the flip-flop to resolve itself to one of the stable states.
		How long does it stay in this state?
		The relative stability of states shown in the figure above shows that the logic 0 and logic 1 states (being at the base of the hill) are much more stable than the somewhat stable state at the top of the hill. In theory, a flip-flop in this quasi-stable hilltop state could remain there indefinitely but in reality it won't. Just as the slightest air current would eventually cause a ball on the illustrated hill to roll down one side or the other, thermal and induced noise will jostle the state of the flip-flop causing it to move from the quasi-stable state into either the logic 0 or logic 1 state.
		What are the cases in which metastability occurs?
		As we have seen that whenever setup and hold violation time occurs, metastability occurs, so we have to see when signals violate this timing requirement:
		When the input signal is an asynchronous signal. When the clock skew/slew is too much (rise and fall time are more than the tolerable values). When interfacing two domains operating at two different frequencies or at the same frequency but with different phase. When the combinational delay is such that flip-flop data input changes in the critical window (setup+hold window)
		What is MTBF?
		MTBF is Mean time between failure, what does that mean? Well MTBF gives us information on how often a particular element will fail or in other words, it gives the average time interval between two successive failures. The figure below shows a typical MTBF of a flip-flop and also it gives the MTBF equation. I am not looking here to derive MTBF equation :-)
		Normally,
		We can use a metastable hardened flip-flop Cascade two or three D-Flip-Flops (two or three stages synchronizer).
		METASTABILITY REFERENCES
		http://www-s.ti.com/sc/psheets/sdya006/sdya006.pdf Thomas J. Chaney, "Measured Flip-Flop Responses to Marginal Triggering", IEEE Transactions on Computers, Vol. C-32. No. 12, December 1983, pp.1207-1209. Lindsay Kleeman and Antonio Cantoni, "On the Unavoidability of Metastable Behavior in Digital Systems", IEEE Transactions on Computers, Vol. C-36. No. 1, January 1987, pp.109-112. Lindsay Kleeman and Antonio Cantoni, "Can Redundancy and Masking Improve the Performance of Synchronizers?", IEEE Transactions on Computers, Vol. C-35, No. 7, July 1986, pp.643-646. Cypress Semiconductor, "Are Your PLDs Metastable?, Fax ID: 6403, May 1992, Revised March 6,1997. http://www.cypress.com/pld/pldappnotes.html#pldmeta http://www.xilinx.com/apps/xapp.htm M. Valencia, M. J. Bellido, J. L. Huertas, A. J. Acosta, and S. Sanchez-Solano, "Modular Asynchronous Arbiter Insensitive to Metastability. IEEE Transactions on Computers, 44(12):1456-1461, December 1995

Setup and hold times of an flip-flop

Setup and hold times

Setup time is the minimum amount of time the data signal should be held steady before the clock event so that the data are reliably sampled by the clock. This applies to synchronous circuits such as the flip-flop.

Hold time is the minimum amount of time the data signal should be held steady after the clock event so that the data are reliably sampled. This applies to synchronous circuits such as the flip-flop.

To summarize: Setup time -> Clock flank -> Hold time.

The metastability in flip-flops can be avoided by ensuring that the data and control inputs are held valid and constant for specified periods before and after the clock pulse, called the setup time (t_su) and the hold time (t_h) respectively. These times are specified in the data sheet for the device, and are typically between a few nanoseconds and a few hundred picoseconds for modern devices.

Unfortunately, it is not always possible to meet the setup and hold criteria, because the flip-flop may be connected to a real-time signal that could change at any time, outside the control of the designer. In this case, the best the designer can do is to reduce the probability of error to a certain level, depending on the required reliability of the circuit. One technique for suppressing metastability is to connect two or more flip-flops in a chain, so that the output of each one feeds the data input of the next, and all devices share a common clock. With this method, the probability of a metastable event can be reduced to a negligible value, but never to zero. The probability of metastability gets closer and closer to zero as the number of flip-flops connected in series is increased.

So-called metastable-hardened flip-flops are available, which work by reducing the setup and hold times as much as possible, but even these cannot eliminate the problem entirely. This is because metastability is more than simply a matter of circuit design. When the transitions in the clock and the data are close together in time, the flip-flop is forced to decide which event happened first. However fast we make the device, there is always the possibility that the input events will be so close together that it cannot detect which one happened first. It is therefore logically impossible to build a perfectly metastable-proof flip-flop.

Propagation delay

Another important timing value for a flip-flop (F/F) is the clock-to-output delay (common symbol in data sheets: t_CO) or propagation delay (t_P), which is the time the flip-flop takes to change its output after the clock edge. The time for a high-to-low transition (t_PHL) is sometimes different from the time for a low-to-high transition (t_PLH).

When cascading F/Fs which share the same clock (as in a shift register), it is important to ensure that the t_CO of a preceding F/F is longer than the hold time (t_h) of the following flip-flop, so data present at the input of the succeeding F/F is properly "shifted in" following the active edge of the clock. This relationship between t_CO and t_h is normally guaranteed if the F/Fs are physically identical. Furthermore, for correct operation, it is easy to verify that the clock period has to be greater than the sum t_su + t_h.

source:http://en.wikipedia.org/wiki/Flip-flop_(electronics)

India Year Book 2011 is available in English language for download

Now India Year Book 2011 is available in English language for download.

it contains...

• Economy
• Science & Technology
• Society
• Polity
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• Art & Culture

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source:http://ibpsexamination.blogspot.com/2011/12/download-india-year-book-2011-in.html