Coding Style of Verilog HDL-Modules

Verilog is a one of the famous Hardware Descriptive Languages (HDL). (VHDL is the other one). Verilog langauage syntax very well matches with C language syntax. This is big advantage in learning Verilog. Logic operators, data types, loops are similar to C. In addition to this certain data types which are necessary to describe a hardware are available in Verilog. For example, nets in a schematic or hardware design is refered here as 'wire'. Flip-flops (or in general are called as registers) are defined as type 'reg'.

"module"s are building block of Verilog. Consider any design represented by a block diagram with its inputs and outputs.

Consider a design named "A". Let "Input1" and "Input2" are its inputs. Let "output1" be its output. In verilog we define this design "A" as module "A" and its inputs and outputs become Input/Output (I/O) "ports" of that module. The keyword for declaring the module in Verilog is "module". This keyword should be followed by the name of the module, in this case it is "A". Hence it becomes :module A. Thus complete syntax of declaring or defining a hardware circuit is as follows:


module ();

            input ---- ; // telll which are inputs

            output ---- ; //these are outputs

             ------------------------------

             ------------------------------

           

            --------------------------------

endmodule

Where,

module ==> Verilog keyword to declare a name of the hardware circuit.

 ==> Name of the module i.e. hardware circuit. (Here it is "A").

 ==>  'terminal' is Verilog way of naming I/O ports, here we should specify all inputs and outputs of circuit. Outputs are written first. Why? Answer is "That's how Verilog is !!!!"

input ==> Verilog keyword to tell the Verilog compiler which are inputs of the module in the given list of .

output ==> Verilog keyword to tell the Verilog compiler which are outputs of the module in the given list of .

endmodule ==> Another verilog keyword to tell that module related all definitions are over and this is the end of the module.

; ==> This semi colon represents end of line.

// --> represents start of comment; same as C syntax.

( /*……………………………..*/  are multiple line comment)



So above design "A" can be defined in Verilog as given below:

module A (Output1, Input1, Input2)

                   output Output1;

                   input Input1, Input2;

                    -------------

                    -------------

 endmodule



If above design is a T flip-flop then we can write module description as:



module T_FF(q,clock,reset); // Here q is o/p; must be first

                    //Other control i/pts must be next i.e. clk and reset inputs]

                    -------------

                    --------------

                   

endmodule

Nesting of modules is not allowed in verilog. One module definition can't contain another module definition within the 'module ' and 'endmodule' statements.

Hardware circuit of design "A" can be defined in 3 different ways in Verilog. They are:

1. Gate level modeling

2. Data flow modeling

3. Behavioural modeling