Verilog vs VHDL

Introduction

 

Verilog and VHDL are two industry standard Hardware Description Languages (HDL) that are used in writing programs for electronic integrated circuits (ICs) i.e., ASIC and FPGA. Many system designers face this issue: which HDL language to choose – Verilog or VHDL. The answer is by no means easy or trivial. Both of these languages are widely compared and contrasted without any clearly defined victor. Both of them have their own merits and demerits and have different origins. Both of these languages hold major market shares of hardware description languages being used around the globe. It is difficult to say with certainty which one is better or superior; however, VHDL is older of the two. You can produce robust designs and comprehensive test environments with both languages, for both ASIC and FPGA.  

   

History and Origin of Languages

 

Both Verilog and VHDL have originated from different programming languages and are supported by different schools of thought. VHDL is based on Pascal and Ada, thus characteristics of both of these languages are reflected by VHDL. Verilog, unlike VHDL, is based on C programming language and is relatively new as compared with VHDL. Internet sources claim that Verilog is supported mostly by the HDL programmers with industrial experience and background while VHDL is supported mostly by academic circles.

The development of VHDL was initiated in 1981 by United States Department of Defense (DOD) to address the hardware life cycle crisis. VHDL was developed for US Department of Defense (DOD) to provide a consistent hardware modeling language for documentation of digital hardware designs. It was never meant to design actual hardware; its sole purpose was hardware modeling. Since Verilog HDL was an intellectual property of Gateway Design Automation, which was eventually acquired by Cadence, so to maintain the supposed competitive advantage and distance themselves from any strategic ties to Verilog HDL to avoid any potential competitive control from Cadence, the individual Electronic Design Automation (EDA) companies extended considerable influence, resources and dollars to turn this language into a hardware design language. These same individual EDA companies developed and implemented their own semi-unique versions of the language at different stages of its development and implementation. The reason that these EDA companies did not adopt Verilog HDL is that they all have a basic philosophy which states that they must own all of their core technology which was being violated in case of Verilog as it, being intellectual property of Cadence, was not open to public domain. Besides this the EDA vendors wanted to break Cadence's stranglehold on the software design tool and IC design market by pushing and promoting VHDL, which was an open language. VHDL became IEEE standard 1076 in 1987.VHDL was updated in 1993 and is known today as "IEEE standard 1076 1993".As an IEEE standard, VHDL must undergo a review process every five years or sooner to ensure its ongoing relevance to industry. The first such revision was completed in September 1993.

Unlike VHDL, Verilog has originated from the commercial and industrial world. It was developed as a part of a complete simulation system, which may be utilized for describing digital hardware systems as well. Verilog HDL was launched by Gateway in 1983.Gateway was bought by Cadence in 1989.Cadence had recognized that if Verilog HDL remained a closed language as compared with VHDL the pressures of standardizations would force the industry to VHDL. So Cadence opened Verilog to the public domain in 1991 by officially publishing it. Verilog HDL became IEEE standard in 1995.

source: http://www.fpgarelated.com/showarticle/19.php